Concurrency Revolution: The Hardware Story

Do software developers need to know anything about CPU architecture? They do if they aspire to be performance experts. Modern CPUs behave almost nothing like the sequential Von Neumann machine model we know and love.

This session provides an overview of the architecture of modern CPUs, how this has changed in recent years, and what the implications are for software development and performance management.

Managing software performance used to be a relatively straightforward process. Uniprocessors were the norm, the number of cycles each instruction took to execute was known, and it was mostly a matter of measuring how many instructions you were executing per unit of work – and then reducing that number. The world has changed: The cost of individual instructions varies by several orders of magnitude, depending on how close the data is to the CPU, and improvements in throughput depend on effective use of parallelism. But to design and analyze performant programs, we have to understand something about the underlying hardware and how that has changed in recent years.

For example, a cache miss may take hundreds of cycles and a cache hit only a fraction of a cycle. That two-orders-of-magnitude spread can make relatively small code changes with significant performance consequences; data indirection is more expensive than it looks. (Advances in compiler technology have mostly removed the costs associated with code indirection, but data inlining hasn't moved out of academia yet.)

This session provides an overview of the architecture of modern CPUs, how this has changed in recent years, and what the implications are for software development and performance management.

About Brian Goetz

Brian Goetz has been a professional software developer for 20 years. He is the author of over 75 articles on software development, and his book, Java Concurrency In Practice, was published in May 2006 by Addison-Wesley. He serves on the JCP Expert Groups for JSRs 166 (concurrency utilities), 107 (caching), and 305 (annotations for safety analysis). He is a frequent presenter at JavaOne, OOPSLA, JavaPolis, SDWest, and the No Fluff Just Stuff Software Symposium Tour. Brian is a Sr. Staff Engineer at Sun Microsystems.

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